“Moore's law” essentially describes the fundamental relationship between technological progress in the semiconductor arts and its commercial applications. According to one version of Moore's law, continually reduced transistor size (approximately a 60% critical dimension reduction every 18 months) and continually increased wafer size has resulted in the persistent decline of semiconductor integrated circuit “per unit cost”. The history of the computing industry over the past 35-40 years serve as a proof of Moore's law in which shipped volume continually expands while per unit cost continually falls.
Over the course of the 1960s, 1970s and into the 1980s, the growth of the industry depended on low volume, highly expensive mainframe computers that were only affordable to large organizations such as major corporations and government institutions. From the 1980s through the 1990s the primary growth market of the industry shifted into higher volume but less expensive personal computers targeted for most desktops (home or office) in the industrialized world.
Currently, in the mid 2000s, another shift is underway in which the growth of the industry is expected to depend (often wirelessly) on commodity-like computing systems that are shipped in extraordinarily high volumes and are priced at extraordinarily low prices. This new era, referred to by some as the “ubiquitous computing” era, is expected to transfer the focus of new uses for computing intelligence from approximately every person (as with the personal computer) to potentially almost any object.
Traditional perspectives are therefore being challenged that computing system intelligence is too expensive to implement in certain “cost sensitive” applications. Examples include, to list just a few, smart electricity meters that transmit a home's electricity usage to a utility company, smart refrigerators that can download the identity of its contents to its owner's personal digital assistant while the owner is shopping in the grocery store; and, smart automobile dashboards that can track a car's GPS location and dynamically provide correct driving instructions to a specific destination.
Another “ubiquitous computing” application is Radio Frequency IDentification (RFID) tags. An RFID tag is a semiconductor chip that can positively respond to a wireless signal that inquires into the RFID tag's existence. RFID tags are expected to be applied at least to automated inventory management and distribution systems. As an example, after affixing an RFID tag to a pallet, the pallet will be able to wirelessly identify itself so as to enable the ability to track its whereabouts or manage its logistical transportation in an automated fashion.
RFID tags, like other solutions for the ubiquitous computing era, are sensitive to costs of production. Here, the less expensive an RFID tag, the easier it is to justify the expense of distributing RFID tags amongst goods that are warehoused and/or transported. In order to improve the cost structure of an RFID tag, its cost of manufacturing must be understood.
RFID tags, being semiconductor chips, are manufactured on wafers each containing many discrete RFID tag chips. If the RFID tag chips from a same wafer are not functionally tested for the first time until after they have been diced from the wafer and individually packaged, the expense of packaging the portion of chips that ultimately fail their functional test is pure economic waste. Therefore it behooves the RFID tag manufacturer to eliminate this waste through “on wafer” functional testing.
On wafer functional testing is the functional testing of semiconductor chips that have not yet been diced into individual chips from their corresponding wafer. FIG. 1a shows a traditional wafer 100 that has been organized into multiple identical patterns, each consisting of geometric data present on a mask set, or “reticle”. (Though the term “reticle” literally applies to the tooling used to pattern the wafer, herein we shall use the term to signify the portion of a wafer uniquely fabricated from this pattern, for expediency.) A single reticle 101 has been shaded in FIG. 1a. Each reticle typically contains multiple semiconductor chips (often identically designed). Breaking down the design of the wafer as a whole into an array of reticles allows for “step-and-repeat” processes that are applied to the wafer during the manufacture of its semiconductor chips (e.g., photolithography).
Referring to FIG. 1b, when the chips on the semiconductor wafer 100 are ready to be tested, a tester 103 applies and receives test signals through a wafer test probe 102. A wafer test probe 102 is a special fixture that is designed to land on specific “landing pads” that have been manufactured on the wafer 100 for the purpose of receiving and/or sending test signals from/to the tester 103 to/from the wafer 100. Based on the results observed by the tester 103 in response to the signals applied by the tester 103, the tester identifies defective chips. The defective chips are identified as scrap, and, as a consequence, any packaging and further testing costs associated with their production is avoided.